![]() I search in Google, NI forum, and decide to use for loop and loop timer in FPGA.ġ. I want to realize that, for example, with time sequence t1, t2, t3, t4, DO outputs T, F, T, F, AO1 outputs A1, A2, A3, A4, AO2 outputs B1, B2, B3, B4, and the delay of AO1 and AO2 should as small as possible(AO1 and AO2 may comes from difference modules). I attach my test project for explanation. ![]() I'm a beginner in labview, and now test cRIO about two weeks.
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